Interconnects have been, are, and will continue to be a limiting factor for the performance and cost of integrated circuits. As technology scales down further, the problems associated with interconnects become ever more pressing. The introduction of low-resistive copper as an alternative interconnect material for aluminum presents researchers with some new challenges, since copper cannot be implemented in the same manner as aluminum alloys.
As feature sizes shrink, narrower copper trenches need to be formed. Also to facilitate closer packing and multilevel connections, trenches are getting proportionally deeper as they get narrower. These deep trenches etched into the dielectric must be filled completely, without voids or defects. With current technology, the deeper the trench, the more likely there will be defects.
“Dual-Damascene” methods are currently used to etch the trenches, fill them electrolytically, then mechanically polish away the excess metal using a chemically active slurry. Etching and filling narrow structures with high aspect ratios will be especially difficult for dual-Damascene architectures.
The challenge is to address narrower trenches; the goal is to make trenches having a width of about 20 to 30 nm, with an aspect ratio of 10 to 1 (ratio length to width).
The Semiconductor Industry Association's most recent National Technology Roadmap predicts that new lithography methods will be able to go as far as a trench width of 50 nm to 60 nm with an aspect ratio of 3 to 1 by 2006.